USB 2.0 PHY IP Device/Host/OTG/Hub (Silicon proven in TSMC 40LP /LL)
Hi-Speed USB interfacing
Soft Mixed Signal Corporation USB 2.0 PHY IP Cores
USB3300 USB HS Board USB high-speed PHY device for ULPI interface
PCIe/USB/SATA PHY Appilcation example | Renesas
USBPHYC internal peripheral - stm32mpu
USB 2.0 PHY for SoC Designs | Cadence IP
USB 2.0 Device Controller for SoC Designs | Cadence IP
USB 2.0/HSIC PHY (Host/Device/OTG/Hub) - IP Solution - INNOSILICON
USB 2.0 PHY Verification
HSIC USB 2.0 PHY IP
Figure 2 from Verilog synthesis of USB 2.0 full-speed device PHY IP | Semantic Scholar
PCIe/USB/SATA PHY Appilcation example | Renesas
Corigine Unveils First Certified SuperSpeed+ USB 3.1 Gen 2 IP with M31 28nm PHY | audioXpress
High Speed Inter-CHIP USB 2.0 PHY | Arasan Chip Systems
USB Universal Serial Bus
The Next-Generation Interconnect | Mouser
Usb3300 USB HS Board Host OTG Phy ULPI Development Communication Module Kit for sale online | eBay
USB 2.0 Solutions | Arasan Chip Systems
USB 2.0 PHY IP core | Arasan Chip Systems
DWTB: USB High Speed Inter-Chip (HSIC) IP: What is it? And why should I use it?
USB3300 USB HS Board Host OTG PHY Low Pin ULPI Evaluation Development Module Kit|Computer Cables & Connectors| - AliExpress
