DWTB: How to Connect Your DesignWare USB 2.0 nanoPHY to Your DesignWare USB 2.0 OTG Controller
USB 3.2 Helps Deliver on Type-C Connector Performance Potential - SemiWiki
Upgrade Your SoC Design With USB4 IP
Delivering on the Promise of Guaranteed Isochronous Traffic in USB 3.1 — Synopsys Technical Article | ChipEstimate.com
USB 2.0 Device Controller
DWTB: How to Connect Your DesignWare USB 2.0 nanoPHY to Your DesignWare USB 2.0 OTG Controller
USB IP University | Interface IP | DesignWare IP | Synopsys
USB 3.1: Physical, Link, and Protocol Layer Changes — Synopsys Technical Article | ChipEstimate.com
Synopsys readies 10Gbit/s USB 3.1 IP and verification support
3.2.4.18. USB DWC3 — Processor SDK Linux Documentation
Synopsys Demonstrates USB 3.2 with Throughput Speeds Up to 20 Gbps | TechPowerUp Forums
USB 2.0 On-The-Go Controller IP Core
Untangling the USB, MIPI & DisplayPort Specifications — Synopsys Technical Article | ChipEstimate.com
Synopsys Demonstrates USB 3.2 with Throughput Speeds Up to 20 Gbps | TechPowerUp
Simplifying USB Software Development with Linux Drivers — Synopsys Technical Article | ChipEstimate.com
USB - Kobol Wiki
USB High Speed Inter-Chip (HSIC) IP: What is it? And why should I use it? - 摩斯电码 - 博客园
ASMedia Demos USB 3.2 Gen 2x2 PHY, USB 3.2 Controller Due in 2019
Device Controllers
Synopsys readies 10Gbit/s USB 3.1 IP and verification support
Upgrade Your SoC Design With USB4 IP
Synopsys' DesignWare IP for USB and PCI Express. | IT Eco Map & News Navigator
Synopsys Expands Multi-Die Solution Leadership with Industry's Lowest Latency Die-to-Die Controller IP
