USB 2.0 Solutions | Arasan Chip Systems
Physical layer - Wikipedia
USB 2.0 Device Controller IP Core (USB20SF)
USB 2.0 Full High Speed Solution | NXP Semiconductors
High Speed Inter-CHIP USB 2.0 PHY | Arasan Chip Systems
Difference between USB and ULPI - Electrical Engineering Stack Exchange
USB-IF certified solutions for USB type-C and Power Delivery - STMicroelectronics
Chip controls up to seven USB-C ports, and Power Delivery
USB 3.0 PHY for SoC Designs | Cadence IP
Mixed-Signal Verification for USB 2.0 Physical Layer IP
TUSB1210 data sheet, product information and support | TI.com
EETimes - New FPGA-based USB 3.0 SuperSpeed Device Controller From SLS
USB 2.0/HSIC PHY (Host/Device/OTG/Hub) - IP Solution - INNOSILICON
Figure 2 from Verilog synthesis of USB 2.0 full-speed device PHY IP | Semantic Scholar
DWTB: USB High Speed Inter-Chip (HSIC) IP: What is it? And why should I use it?
Soft Mixed Signal Corporation USB 2.0 PHY IP Cores
USB Communicator
Usb3300 High Speed Usb Host Device Or Otg Phy 2.0 3.3v T/r 32-pin Qfn Ep Ic Chip Usb3300-ezk-tr - Buy Usb3300-ezk-tr,Usb3300,Usb3300 High Speed Usb Host Device Or Otg Phy 2.0 3.3v T/r
ASMedia Demos USB 3.2 Gen 2x2 PHY, USB 3.2 Controller Due in 2019
ULPI - Kcchao
Physical layer - Wikiwand
Standalone USB Transceiver Chip - EEWeb
HSIC USB 2.0 PHY IP
